View MP28257DD_7495766.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mp28257 4a, fast transient, 4.2v-to-20v input synchronous step-down converter 2mmx3mm qfn12 mp28257 rev 1.0 www.monolithicpower.com 1 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. the future of analog ic technology description the mp28257 is a fully-integrated, synchronous, step-down, switch-mode converter with a programmable frequency. it offers a very compact solution that can provide up to 4a of continuous output current over a wide input supply range with excellent load and line regulation, and can operate at high efficiency over a wide output current load range. constant-on-time control mode provides fast transient response and eases loop stabilization. protections include short-circuit protection, over-current protection, over-voltage protection, under-voltage protection, and thermal shut down. the mp28257 requires a minimal number of readily-available standard external components. the device is available in a space saving 2mmx3mm qfn12 package that complies with rohs. features ? wide 4.2v-to-20v operating input range ? 4a continuous output current ? internal 120m ? high-side, 50m ? low- side power mosfets ? stable with ceramic output capacitors ? proprietary switching loss-reduction technology ? power-good indicator ? soft startup/shutdown ? programmable switching frequency ? scp, ocp, ovp, uvp protection and thermal shutdown ? output adjustable from 0.815v to 13v ? available in a 2mmx3mm qfn12 package applications ? networking systems ? distributed power systems for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 2 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. ordering information part number ocp protection package top marking free air temperature (t a ) MP28257DD* latch-off mode qfn12 (2x3mm) abf -40c to +85c * for tape & reel, add suffix ?z (e.g. MP28257DD?z). for rohs compliant packaging, add suffix ?lf (e.g. MP28257DD?lf?z) package reference gnd sw bst vcc en gnd sw in freq fb top view pg gnd 1 2 12 3 4 8 7 6 5 11 10 9 sw qfn12 (2x3mm) absolute maxi mum ratings (1) supply voltage v in ....................................... 22v v sw ..................................... -0.3v to (v in + 0.3v) v bst ........................................................ v sw +6v all other pins ................................... -0.3v to +6v continuous power dissipation (t a = 25c) (2) qfn12 (2x3mm) ........................................ 1.8w junction temperature .............................. 150c lead temperature .................................... 260c storage temperature ............... -65c to +150c recommended operating conditions (3) supply voltage v in ........................... 4.2v to 20v output voltage v out ..................... 0.815v to 13v maximum junction temp. (t j ) .................. 125c thermal resistance (4) ja jc qfn12 (2x3mm) ..................... 70 ...... 15 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 3 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. electrical characteristics v in = 12v, t a = 25c, unless otherwise noted. parameters symbol condition min typ max units supply current (shutdown) i in v en = 0v 1 a supply current (quiescent) i in v en = 2v, v fb = 0.9v 360 a hs switch-on resistance ( 5 ) hs rds-on 120 m ? ls switch-on resistance ( 5 ) ls rds-on 50 m ? switch leakage sw lkg v en = 0v, v sw = 0v or 12v 0 10 a current limit i limit after soft-start time-out 5.5 7 a one-shot on time t on r7 = 300k ? , v out = 1.2v 250 ns minimum off time t off 130 150 ns fold-back off time ( 5 ) t fb i lim = 1 4.5 s ocp hold-off time ( 5 ) t oc i lim = 1 50 s feedback voltage v fb t a = 25c 807 815 823 mv t a = -40c to 85c 803 827 mv feedback current i fb v fb = 800mv 10 50 na soft start time t ss 1 ms en rising threshold en vth-hi 1.05 1.35 1.6 v en threshold hysteresis en vth-h y s 500 mv en input current i en v en = 2v 2 a v en = 0v 0 en input current i en v en =2v 2 a v en =0v 0 power-good rising threshold pg vth-hi power-good 90 % power-good falling threshold pg vth-lo fault condition 85 % power-good delay pgtd 500 s power-good sink current i pg pg = 0.4v 4 ma power-good leakage current i pg leak v pg = 3.3v 10 na vin under-voltage lockout threshold rising inuv vth 3.1 v vin under-voltage lockout threshold hysteresis inuv hys 300 mv thermal shutdown ( 5 ) t sd 150 c thermal shutdown hysteresis ( 5 ) t sd-hys 25 c note: 5) guaranteed by design.
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 4 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. pin functions qfn12 (2x3mm) pin # name description 9 in supply voltage. the mp28257 operates from a 4.2v to 20v input rail. c1 decouples the input rail. use wide pcb traces and mu ltiple vias to make the connection. 1, 11, 12 gnd system ground. reference ground for t he regulated output voltage. these pins require special consideration during pcb layout. 2, 10, exposed pad sw switch output. connect with wide pcb traces. 3 bst bootstrap. requires a capacitor connec ted between sw and bst pins to form a floating supply across the high-side switch driver. 4 vcc internal bias supply. decouple with a 1f ceramic capacitor as close to the pin as possible. 5 en en = 1 to enable the mp28257. for automatic start-up, connect en pin to vin with a pull-up resistor. 7 fb feedback. sets the output voltage when connec ted to the tap of an external resistor divider, connected between output and gnd. 8 freq frequency. set during ccm operation. connect a resistor r7 to in to set the switching frequency. decouple with a 1nf capacitor. 6 pg power-good output. the output of this pin is an open drain that goes high if the output voltage is higher than 90% of the nominal voltage. there is a 0.5ms delay between when the feedback exceeds 90% to when the pg pin goes high.
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 5 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. typical performanc e characteristics v in = 12v, v out = 1.2v, l = 2 h , t a = 25c, unless otherwise noted.
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 6 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. typical performanc e characteristics (continued) v in = 12v, v out = 1.2v, l = 2 h , t a = 25c, unless otherwise noted. v in /ac 100mv/div. v out /ac 10mv/div. v out 1v/div. v sw 5v/div. i l 5a/div. input/output voltage ripple i out = 4a v in 10v/div. v sw 10v/div. i l 1a/div. v out 1v/div. v in 10v/div. v sw 10v/div. i l 5a/div. start up through vin i out = 0a start up through vin i out = 4a shutdown through vin i out = 0a shutdown through vin i out = 4a start up through en i out = 0a start up through en i out = 4a shutdown through en i out = 0a shutdown through en i out = 4a v out 1v/div. v in 10v/div. v sw 2v/div. i l 1a/div. v out 1v/div. v in 5v/div. v sw 5v/div. i l 5a/div. v out 1v/div. v en 5v/div. v sw 10v/div. i l 1a/div. v out 1v/div. v en 5v/div. v sw 10v/div. i l 5a/div. v out 1v/div. v en 5v/div. v sw 10v/div. i l 1a/div. v out 1v/div. v en 5v/div. v sw 10v/div. i l 5a/div.
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 7 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. typical performanc e characteristics (continued) v in = 12v, v out = 1.2v, l = 2 h , t a = 25c, unless otherwise noted. v out /ac 50mv/div. i l 2a/div. i l 5a/div. v out /ac 50mv/div. v sw 10v/div. i l 5a/div. v out /ac 50mv/div. v sw 10v/div.
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 8 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. block diagram start - + + - + - + - + soft start/stop freq vcc 5v ldo ilim oc q vcc sw gnd 0 vcc in bst rsen ls driver hs driver ls _ fet hs _ fet pwm logic xs xr over-current timer current sense amplifer current modulator uv ov uv detect comparator ov detect comparator off timer on timer hs iiimit comparator loop comparator en 1.0v 0.8v 1meg 0.4v 0 fb pgood comparator reference pg + - - + figure 1: functional block diagram
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 9 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. operation pwm operation the mp28257 is a fully-integrated, synchronous, rectified, step-down switch converter. the device uses constant-on-time (cot) control to provide fast transient response and easy loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) turns on whenever the feedback voltage (v fb ) is lower than the reference voltage (v ref )?a low v fb indicates insufficient output voltage. the input voltage and the frequency-set resistor determine the on period as follows: 7 on in 9.3 r (k ) t(ns) 40ns v(v) 0.4 ?? ?? ? (1) after the on period elapses, the hs-fet enters the off state. by cycling the hs-fet between the on and off states, the converter regulates the output voltage. the integrated low-side mosfet (ls-fet) turns on when the hs-fet is in its off state to minimize the conduction loss. shoot-through occurs when there is both the hs- fet and ls-fet are turned on at the same time, causing a dead short between input and gnd. shoot-through dramatically reduces efficiency, and the mp28257 avoids this by internally generating a dead-time (dt) between when the hs-fet is off and the ls-fet is on, and when the ls-fet is off and the hs-fet is on. the device enters either heavy-load operation or light-load operation depending on the amplitude of the output current. heavy-load operation figure 2: heavy-load operation during heavy-load operation?when the output current is high?the mp28257 enters continuous- conduction mode (ccm) where the hs-fet and ls-fet repeat the on/off operation described for pwm operation, the inductor current never goes to zero, and the switching frequency (f sw ) is fairly constant. figure 2 shows the timing diagram during this operation. light-load operation during light-load operation?when the output current is low?the mp28257 automatically reduces the switching frequency to maintain high efficiency, and the inductor current drops near zero.. when the inductor current reaches zero, the ls-fet driver goes into tri-state (high z). the current modulator controls the ls-fet and limits the inductor current to around -1ma as shown in figure 3. hence, the output capacitors discharge slowly to gnd through ls-fet, r 1 , and r 2 . this operation greatly improv es device efficiency when the output current is low. figure 3: light-load operation light-load operation is also called skip mode because the hs-fet does not turn on as frequently as during heavy-load conditions. the frequency at which the hs-fet turns on is a function of the output current?as the output current increases, the time period that the current modulator regulates becomes shorter, and the hs-fet turns on more frequently. the switching frequency increases in turn. the output current reaches the critical level when the current modulator time is zero, and can be determined using the following equation: in out out out sw in (v v ) v i 2lf v ?? ? ? ?? (2) the device reverts to pwm mode once the output current exceeds the critical level. after that, the switching frequency stays fairly constant over the output current range.
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 10 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. bs t n 1 lsg vc c c 3 s w l c o u t c 5 figure 4: floating driver and bootstrap charging the floating power mosfet driver is powered by an external bootstrap capacitor. this floating driver has its own uvlo protection with a rising threshold of 2.2v and a hysteresis of 150mv. the bootstrap capacitor is charges from vcc through n1 (figure 4): n1 turns on when the ls- fet turns on, and turns off when the ls-fet turns off. switching frequency the mp28257 uses cot control because there is no dedicated oscillator in the ic. the input voltage is feed-forwarded to the on-time one-shot timer through the resistor r 7 . the duty ratio is kept as v out /v in , and the switching frequency is fairly constant over the input voltage range. the switching frequency can be determined with the following equation: 6 sw 7in delay in out 10 f(khz) 9.3 r (k ) v (v) t(ns) v(v) 0.4 v (v) ? ?? ?? ? (3) where t delay is the comparator delay, and equals approximately 40ns. the mp28257 is optimized to operate at a high switching frequency a high efficiency. the high switching frequency makes it possible to use small-sized lc filter components to save system pcb space. ramp compensation jitter occurs in both pwm and skip modes when noise in the v fb ripple propagates a delay to the hs-fet driver, as shown in figures 5 and 6. jitter can affect system stability, with a noise immunity proportional to the steepness of the v fb ?s downward slope. however, the v fb ripple does not directly affect noise immunity. v re f v fb hs driver v noise j itter v s l o pe1 figure 5: jitter in pwm mode v fb hs driver jitter v ref v slope2 v noise figure 6: jitter in skip mode when using ceramic output capacitors, the esr ripple is not sufficient to stabilize the system, and the system requires external ramp compensation. i i fb i c4 i r4 i fb figure 7: simplified circuit in pwm mode with external ramp compensation figure 7 shows a simplified external ramp compensator (r4 and c4) for pwm mode, with hs-fet off. chose r1, r2, and c4 of the external ramp to meet the following condition: 12 sw 4 1 2 rr 11 2f c 5rr ?? ? ?? ?? ?? ? ? ?? (4)
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 11 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. where: r4 c4 fb c4 iiii ??? (5) the downward slope of the v fb ripple can be estimated as: out slope1 44 v v rc ? ? ? (6) reducing either r4 or c4, as seen from equation (6), can control some of the instability in pwm mode. if the condition from equation (4) prevents reductions to c4, then only reduce r4. v slope1 has an expected range between 20v/ms to 40v/ms based on bench experiments. the external ramp is not necessary for other types of capacitors with higher esr such as poscaps. figure 8: simplified circuit in pwm mode without external ramp compensation figure 8 shows the equivalent circuit in pwm mode, with the hs-fet off, and without an external ramp circuit. the esr ripple dominates the output ripple. the downward slope of the v fb ripple is: ref slope1 esr v v l ?? ? (7) designing v slope1 ?with a recommended range between 15v/ms to 30v/ms based on bench experiments?requires using the minimum esr value of the output capacitor with a small-value inductor. an external ramp does not affect v slope2 in skip mode. figure 9 shows an equivalent circuit with hs-fet off and the current modulator regulating the ls-fet. instead, the downward slope of the v fb ripple can be modeled with the following equation that excludes i mod : ?? ref slope2 12 out v v rr c ? ? ?? (8) figure 9: simplified circuit in skip mode to keep the system stable during light load condition, the use fb resistors in the range of 5k ? to 50k ? . keep the v slope2 value between 0.4mv/ms to 0.8mv/ms. soft start/stop mp28257 employs a soft-start/stop (ss) mechanism to ensure a smooth output during power up and power shut-down. when the en pin goes high, the internal ss voltage slowly ramps up. the output voltage smoothly ramps up with the ss voltage. once ss voltage rises above the v ref , it continues to ramp up while the pwm comparator only compares the v ref and the fb voltage. at this point, the soft-start finishes and it enters steady state operation. the ss time is set about 1ms internally. when the en pin goes low, an internal current source discharges the internal ss voltage. once the ss voltage falls below the v ref , the pwm comparator will only compare the v ref to the ss voltage. the output voltage then decreases smoothly with the ss voltage until the voltage level zeros out. power-good (pg) the pg pin is the open drain of a mosfet that connects to vcc or some other voltage source through a resistor (e.g.. 100k ? ). the mosfet turns on with the application of an input voltage
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 12 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. so that the pg pin is pulled to gnd before ss is ready. after fb voltage reaches 90% of v ref , the pg pin is pulled high after a 0.5ms delay. when the fb voltage drops to 70% of v ref , the pg pin will be pulled low. over-current protection (ocp) and short- circuit protection (scp) mp28257 has cycle-by cycle over-current limit control. it monitors the inductor current during the on state. once the inductor current exceeds the current limit, the hs-fet turns off and the ocp timer?set at 50 s?starts. the ocp triggers. if the inductor current reaches or exceeds the current limit every cycle if in those the 50 s, the device enters latch-off mode the mp28257 scp triggers when dead shorts occur?when the inductor current exceeds the current limit and the fb voltage is lower than 50% of the v ref ?and will trigger the ocp. the mp28257 needs power cycle to restart after it triggers ocp or scp. over/under-voltage protection (ovp/uvp) mp28257 monitors the output voltage through a resistor-divided fb voltage to detect over- and under-voltage on the output. when the fb voltage is higher than 125% of the v ref , it triggers the ovp. once it triggers the ovp, the ls-fet is always on while the hs-fet is off. it needs to power cycle to turn on again. conversely, the uvp triggers when the fb voltage falls below 50% of v ref (0.815v). usually uvp accompanies a drop in the current limit and this results in scp. uvlo protection mp28257 has under-voltage lock-out (uvlo) protection. the mp28257 powers up when the input voltage exceeds the uvlo rising threshold voltage. it shuts off when the input voltage falls below the uvlo falling threshold voltage. this is non-latch protection. thermal shutdown the mp28257 employs thermal shutdown by internally monitoring the junction temperature of the ic. if the junction temperature exceeds the threshold value (typically 150c), the converter shuts off. this is non-latch protection. there is about 25c hysteresis. once the junction temperature drops around 125c, it initiates a soft start.
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 13 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. application information setting the output voltage the output voltage is set by using a resistive voltage divider from the output voltage to the fb pin. the use of low-esr ceramic output capacitors requires adding an external voltage ramp to the fb through r4 and c4. choose an r2 value between 5k ? and 40k ? , then determine r1 using the following equation: 1 ref ramp 4 2outref ramp 1 r 1 vv 1 2 1 r r(v v v ) 2 ? ? ? ??? (9) using the v ramp value derived from equation (16). for example feedback resistor values and output voltages, see the design example section on page 15. input capacitor the input current to the step-down converter is discontinuous and therefore requires a capacitor to supply the ac current to the step-down converter while maintaining the dc input voltage. ceramic capacitors are recommended for best performance and should be placed as close to the v in pin as possible. use capacitors with x5r and x7r ceramic dielectrics because they are fairly stable with temperature fluctuations. the capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated as follows: out out cin out in in vv ii (1 ) vv ?? ?? (10) the worst-case condition occurs at v in = 2v out , where: out cin i i 2 ? (11) for simplification, choose the input capacitor with an rms current rating greater than half of the maximum load current. the input capacitance value determines the input voltage ripple of the converter. if there is an input voltage ripple requirement in the system, choose the input capacitor that meets the specification. the input voltage ripple can be estimated as follows: out out out in sw in in in iv v v(1) fc v v ?? ? ?? ? (12) under worst-case conditions where v in = 2v out : out in sw in i 1 v 4f c ??? ? (13) output capacitor the output capacitor is required to maintain the dc output voltage. ceramic or poscon capacitors are recommended. the output voltage ripple can be estimated as: out out out esr sw in sw out vv 1 v(1)(r ) fl v 8fc ?? ?? ? ? ??? (14) where r esr is esr value of c out . for ceramic capacitors, the capacitance dominates the impedance at the switching frequency and is the primary contributor to the output voltage ripple. for simplification, the output voltage ripple can be estimated by: out out out 2 sw out in vv v(1) 8f lc v ?? ?? ??? (15) the output voltage ripple caused by esr is very small for ceramic capacitors, so it needs an external ramp to stabilize the system. the voltage ramp is expected to be around 30mv. the external ramp can be generated through resistor r4 and capacitor c4, using the following equation: in out on ramp 44 (v v ) t v rc ?? ? ? (16) the c4 should meet the following requirement: 12 sw 4 1 2 rr 11 () 2f c 5rr ? ?? ?? ? ? (17) in the case of poscon capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr is high enough to stabilize the system, and does not require an external ramp. a minimum esr value of 12m ? is recommended to ensure stable operation of the converter. for simplification, the output ripple can be approximated as:
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 14 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. out out out esr sw in vv v(1)r fl v ?? ?? ? ? (18) inductor the inductor is necessary to supply constant current to the output load while being driven by the switched input voltage. a larger-value inductor will result in less ripple current that will result in lower output ripple voltage. however, a larger-value inductor will have a larger physical footprint, higher series resistance, and/or lower saturation current. a good rule for determining the inductance value is to design the peak-to- peak ripple current in the inductor to be in the range of 30% to 40% of the maximum output current, and that the peak inductor current is below the maximum switch current limit. the inductance value can be calculated by: out out sw l in vv l(1) fi v ??? ?? (19) where i l is the peak-to-peak inductor ripple current. the inductor should not saturate under the maximum inductor peak current, where the peak inductor current can be calculated by: out out lp out sw in vv ii (1 ) 2f l v ?? ?? ? (20) design example some design examples with typical outputs are provided below: table 1: 1.2v vout (l = 2 h) v in (v) v out (v) c1 r7 ( ? ) r4 ( ? ) c4 (f) r1 ( ? ) r2 ( ? ) f sw (hz) 12 1.2 10 f*1 300k 499k 220p 12.1k 24.3k 450k 5 1.2 10 f*1 300k 390k 220p 12.1k 24.3k 440k 3.3 1.2 10 f*1 300k 243k 220p 12.1k 24.3k 435k table 2: 1.8v vout (l = 2 h) v in (v) v out (v) c1 r7 ( ? ) r4 ( ? ) c4 (f) r1 ( ? ) r2 ( ? ) f sw (hz) 12 1.8 10 f*1 402k 499k 220p 30.1k 24.3k 480k 5 1.8 10 f*1 402k 390k 220p 30.1k 24.3k 460k 3.3 1.8 10 f*2 402k 280k 220p 30.1k 24.3k 450k note: for 1.8v v out from 3.3v v in , a larger c1 is recommended to sustain maximum 4a load. table 3: 2.5v vout (l = 4.2 h) v in (v) v out (v) c1 r7 ( ? ) r4 ( ? ) c4 (f) r1 ( ? ) r2 ( ? ) f sw (hz) 12 2.5 10 f*1 500k 453k 390p 21.5k 10k 500k 5 2.5 10 f*1 500k 453k 390p 21.5k 10k 500k table 4: 3.3v vout (l = 6.5 h) v in (v) v out (v) c1 r7 ( ? ) r4 ( ? ) c4 (f) r1 ( ? ) r2 ( ? ) f sw (hz) 12 3.3 10 f*1 680k 470k 330p 31.6k 10k 500k 5 3.3 10 f*1 680k 470k 330p 31.6k 10k 500k table 5: 5v vout (l = 8.8 h) v in (v) v out (v) c1 r7 ( ? ) r4 ( ? ) c4 (f) r1 ( ? ) r2 ( ? ) f sw (hz) 12 5 10 f*1 1m 750k 330p 53.6k 10k 500k the detailed application schematic is shown in figure 10. the typical performance and circuit waveforms have been shown in the typical performance characteristics section. for more possible applications of this device, please refer to related evaluation board data sheets.
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter mp28257 rev 1.0 www.monolithicpower.com 15 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. 301k 40.2k 20k 390pf 340k figure 10: typical application circuit v in =12v, v out =1.2v, i out =4a layout recommendation 1) the high current paths (gnd, in, and sw) should be placed very close to the device with short, wide, and direct traces. 2) put the input capacitors as close to the in and gnd pins as possible. 3) put the decoupling capacitor as close to the v cc and gnd pins as possible. 4) keep the switching node sw short and away from the feedback network. 5) the external feedback resistors should be placed next to the fb pin. make sure that there is no via on the fb trace. 6) keep the bst voltage path (bst, c3, and sw) as short as possible. 7) four-layer layout is recommended to achieve better thermal performance.
mp28257 ?4a, 4.2v-to-20v, fast transie nt, synchronous step-down converter notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp28257 rev 1.0 www.monolithicpower.com 16 11/8/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. package information qfn12 (2x3mm) side view top view bottom view 1.90 2.10 2.90 3.10 0.00 0.05 pin 1 id marking recommended land pattern note: 1) all dimensions are in millimeters . 2) exposed paddle size does not include mold flash . 3) lead coplanarity shall be 0.10 millimeter max. 4) jedec reference drawing is jedec mo -220 5) drawing is not to scale . pin 1 id index area 1 11 7 5 0.45 0.55 0.50 bsc 0.20 0.30 0.35 0.45 0.80 1.00 0.20 ref 6 12 0.35 0.45 0.60 0.50 0.25 1.90 0.70 0.00 1.10 0.35 0.45 0.40 0.35 0.45 0.00 1.30 0.20 0.20 0.30 1.45 0.90 0.25 1.80 0.70 0.25 0.60

▲Up To Search▲

Price & Availability of MP28257DD

	To Download MP28257DD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .